1. Field of the Present Invention
The present invention generally relates to the field of microprocessor-based data processing systems and more particularly to a system and method for efficient handling of processor internal errors in a symmetric multiprocessor server system.
2. History of Related Art
Interrupt handling is well known in the field of microprocessors and microprocessor-based data processing devices. Traditionally, the handling of processor internal errors (IERRs) in a symmetric multiprocessor (SMP) system has been the responsibility of a System management interrupt (SMI) handler. The SMI typically performs the tasks of logging the error condition and setting the appropriate controls to remove the faulty processor from the available resources.
Unfortunately, delegating processor internal error handling to the SMI is problematic. More specifically, the SMI is not immediately available when a server is powered-on. The SMI is usually installed as part of the power on self test (POST). If an internal error occurs before the SMI is installed and functioning, status cannot be reported and the system will probably halt. In addition, relying on the SMI to handler IERRs assumes that at least one of the processor is sufficiently operable to execute the SMI. If this assumption is not met, system behavior is unpredictable and the system will more than likely abort operation with little information to indicate the reason for the failure. Moreover, while it might be tempting to use the service processor found on many server blades to respond to the error and execute the SMI, the response latency of conventional service processors relative to high end SMP servers is too great to ensure that erroneous data is not propagated thereby possibly contaminating stored data records.
It would therefore be highly desirable to implement a data processing system in which processor internal errors are handled expeditiously. It would be further desirable if the implemented solution did not rely on the main processors to handle processor internal errors. It would be still further desirable if the response performance of the implemented solution was compatible with the requirements of high end multiprocessor systems.